Method for driving semiconductor device

ABSTRACT

A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for driving a semiconductor device including a selection circuit and an electronic device including the semiconductor device.

2. Description of the Related Art

In an integrated circuit, a multiplexer is used as a selection circuit for selecting an input signal, for example. The multiplexer is a circuit for outputting one output signal from a plurality of input signals. Here, a reconfigurable logic circuit is described as an example of a semiconductor device including multiplexers.

The reconfigurable logic circuit includes a plurality of logic blocks each including a plurality of logic elements, a plurality of wirings for connecting the logic blocks, a programmable switch, and an input/output block.

The reconfigurable logic circuit can have a logical structure with a high degree of flexibility by changing the function of each logic element or connecting the logic blocks between the wirings. For example, in general, an output of a look-up table in a logic element is selected by a multiplexer to change the logic of the logic element. In that case, the multiplexer has not only a system in which its operation depends on a signal input from the outside but also a system in which its operation depends on data stored in a memory in advance. A circuit including such a memory and a multiplexer is referred to as a programmable multiplexer (see Patent Document 1).

Here, a typical multiplexer structure as disclosed in Patent Document 2 will be described. FIG. 12A shows a two-input and one-output multiplexer including a static random access memory (SRAM), a transistor T11, and a transistor T12. Each of the transistors T11 and T12 controls conduction between an input terminal and an output terminal and is also referred to as a transfer gate. In the transistor T11, one of a source and a drain is connected to an input terminal IN_A, the other of the source and the drain is connected to an output terminal OUT, and a gate is connected to a terminal D of the SRAM. In the transistor T12, one of a source and a drain is connected to an input terminal IN_B, the other of the source and the drain is connected to the output terminal OUT, and a gate is connected to a terminal DB of the SRAM. One of a signal input into the input terminal IN_A and a signal input into the input terminal IN_B is output from the output terminal OUT in accordance with a combination of logic values of selection signals which are held in the SRAM and are output from the terminal D and the terminal DB.

However, in the case where the transistors T11 and T12 are n-channel transistors, a potential of a signal output from the transistor T11 or T12 to the output terminal OUT is lower than one of the potentials of the signals input into the input terminal IN_A and the input terminal IN_B by a threshold voltage of the transistor T11 or T12.

Therefore, it is necessary to make the potential of the terminal D or DB higher than maximum potentials of a signal input into the input terminal IN_A and a signal input into the input terminal IN_B by the threshold voltages or more. This means to increase the power source voltage of the SRAM.

For example, in the case where the maximum potentials of the signals input into the input terminal IN_A and the input terminal IN_B are each +1 V and the threshold voltages of the transistor T11 and the transistor T12 are each +0.5 V, it is necessary to make the potential of the terminal D or DB higher than or equal to +1.5 V. However, in the case where high-speed operation (here, a reduction in the resistance of the multiplexer) is necessary, the potential of the terminal D or DB needs to be higher than or equal to +1.6 V, preferably higher than or equal to +1.7 V. Therefore, the potential of a high-potential node of the SRAM needs to be higher than or equal to +1.6 V, preferably higher than or equal to +1.7 V.

Thus, as shown in FIG. 12B, a method for suppressing change in potential of an output signal from an input signal by using a transmission gate TG1 and a transmission gate TG2 instead of the transistors T11 and T12 is employed.

REFERENCE

-   [Patent Document 1] U.S. Pat. No. 7,030,650 Specification -   [Patent Document 2] U.S. Pat. No. 6,781,865 Specification

SUMMARY OF THE INVENTION

However, the multiplexer shown in FIG. 12B includes the transmission gates TG1 and TG2, which each include two transistors of different conductivity types. Therefore, the area of the multiplexer is increased. In order to make an equivalent amount of current flow through a p-channel transistor and an n-channel transistor, a channel width of the p-channel transistor particularly needs to be increased because the field-effect mobility of the p-channel transistor is about one-third of the field-effect mobility of the n-channel transistor. Thus, the area of the p-channel transistor needs to be about three times as large as the area of the n-channel transistor, for example.

In addition, even when an inverter used for the SRAM is stable, a slight amount of current (standby current) flows between the high-potential node and a low-potential node. The standby current increases significantly with miniaturization of a circuit; therefore, an increase in power consumption in a standby state has been a problem. Note that the standby current increases exponentially to the power source voltage of the inverter.

Particularly in the multiplexer including the transfer gates, which is shown in FIG. 12A, the power source voltage of the SRAM needs to be set higher as described above; therefore, the standby current increases significantly.

Accordingly, one embodiment of the present invention provides a method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption.

One embodiment of the present invention is a method for operating a semiconductor device including a selection circuit that includes a memory and a multiplexer. In the memory, one of a source and a drain of a first transistor is connected to a first capacitor, and one of a source and a drain of a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, one of a source and a drain is connected to a first input terminal and the other of the source and the drain is connected to an output terminal and, in a fourth transistor, one of a source and a drain is connected to a second input terminal and the other of the source and the drain is connected to the output terminal. Further, the method for operating the semiconductor device includes a first step and a second described below. In the first step, a potential (a first potential) which is higher than maximum potentials of a first signal input into the first input terminal and a second signal input into the second input terminal and which can turn on the third transistor regardless of the first signal input into the first input terminal and the second signal input into the second input terminal is held in a first node to which the one of the source and the drain of the first transistor, one of a pair of electrodes of the first capacitor, and a gate of the third transistor are connected, and then a potential which can turn off the fourth transistor regardless of the first signal input into the first input terminal and the second signal input into the second input terminal is held in a second node to which the one of the source and the drain of the second transistor, one of a pair of electrodes of the second capacitor, and a gate of the fourth transistor are connected. In the second step, the first signal is input into the first input terminal and the second signal is input into the second input terminal, and the first signal is output from the output terminal.

Another embodiment of the present invention is a method for operating a semiconductor device including a selection circuit that includes a memory and a multiplexer. In the memory, one of a source and a drain of a first transistor is connected to a first capacitor, and one of a source and a drain of a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, one of a source and a drain is connected to a first input terminal and the other of the source and the drain is connected to an output terminal and, in a fourth transistor, one of a source and a drain is connected to a second input terminal and the other of the source and the drain is connected to the output terminal. Further, the method for operating the semiconductor device includes a first step and a second described below. In the first step, a first potential is held in one of a first node to which the one of the source and the drain of the first transistor, one of a pair of electrodes of the first capacitor, and a gate of the third transistor are connected and a second node to which the one of the source and the drain of the second transistor, one of a pair of electrodes of the second capacitor, and a gate of the fourth transistor are connected, and then a second potential higher than the first potential is held in the one of the first node and the second node. In the second step, a first signal is input into the first input terminal and a second signal is input into the second input terminal, and one of the first signal and the second signal is output from the output terminal.

Note that in the first step, one of the third transistor and the fourth transistor is turned on by holding the first potential in the one of the first node and the second node in such a manner that a signal input into the other of the source and the drain of the first transistor and a signal input into the other of the source and the drain of the second transistor are complementary to each other. Then, the second potential may be held in the one of the first node and the second node in such a manner that a signal input into the other of the source and the drain of the first transistor and a signal input into the other of the source and the drain of the second transistor have the same potentials.

Note that in the first step, a third potential which turns off the other of the third transistor and the fourth transistor may be held in the other of the first node and the second node.

The potentials of the first node and the second node can be held during a period which is necessary (from 10 milliseconds to 10 years) in such a manner that a transistor whose channel region is formed in a wide-gap semiconductor is formed as each of the first transistor and the second transistor connected to the first node and the second node, respectively, and the capacitance of the first capacitor and the capacitance of the second capacitor are set or selected appropriately. Therefore, it is possible to stop supply of power to the semiconductor device when not used; accordingly, power consumption can be reduced. Moreover, it is not necessary to rewrite data to the first node and the second node at the start-up of the semiconductor device; thus, the starting time can be shortened and the power consumption can be reduced.

Further, after the first potential is held in the first node to which the one of the source and the drain of the first transistor, the one of the pair of electrodes of the first capacitor, and the gate of the third transistor are connected or the second node to which the one of the source and the drain of the second transistor, the one of the pair of electrodes of the second capacitor, and the gate of the fourth transistor are connected, the second potential higher than the first potential is held in the first node or the second node, whereby characteristics higher than or equal to those of a transmission gate can be obtained. Accordingly, a p-channel transistor is not necessary and it is possible to reduce the area of the selection circuit.

Furthermore, the gate of the third transistor or the gate of the fourth transistor is supplied with a potential which can turn on the third transistor or the fourth transistor regardless of the potentials of the signals input into the first input terminal and the second input terminal. In one embodiment of the present invention, even without a circuit such as an SRAM, which includes an inverter, it is possible to turn on or off the transistors T3 or T4; therefore, standby current does not flow and power consumption can be reduced greatly.

According to one embodiment of the present invention, it is possible to reduce power consumption of a semiconductor device including a selection circuit, reduce the area of the selection circuit in the semiconductor device, and downsize the size of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a selection circuit of one embodiment of the present invention.

FIG. 2 is a timing chart showing manners for operating a selection circuit of one embodiment of the present invention.

FIGS. 3A and 3B are circuit diagrams showing manners for operating a selection circuit of one embodiment of the present invention.

FIG. 4 is a circuit diagram showing a manner for operating a selection circuit of one embodiment of the present invention.

FIGS. 5A and 5B are block diagrams showing a semiconductor device of one embodiment of the present invention.

FIG. 6 shows examples of output waveforms of selection circuits.

FIGS. 7A and 7B are block diagrams showing a semiconductor device of one embodiment of the present invention.

FIGS. 8A and 8B are top views illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 9A and 9B are top views illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.

FIGS. 12A and 12B are circuit diagrams each illustrating a conventional selection circuit.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Accordingly, the present invention should not be construed as being limited to the description of the embodiments below.

Note that functions of the “source” and “drain” may be switched in the case where transistors of different polarities are employed or in the case where the direction of a current flow changes in a circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification.

In addition, even when a circuit diagram shows independent components as if they are electrically connected to each other, there is actually a case where one conductive film has functions of a plurality of components such as a case where part of a wiring also functions as an electrode. The “electrical connection” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

Note that the position, size, range, or the like of each component in drawings and the like is not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like as disclosed in the drawings and the like.

The ordinal number such as “first”, “second”, and “third” are used in order to avoid confusion among components.

Embodiment 1

In this embodiment, one embodiment of a semiconductor device including a selection circuit and a method for driving the semiconductor device will be described with reference to FIG. 1, FIG. 2, FIGS. 3A and 3B, and FIG. 4.

FIG. 1 is a circuit diagram of a selection circuit PMUX including a memory MEM and a multiplexer MUX.

In FIG. 1, the memory MEM includes a transistor T1, a capacitor C1, a transistor T2, and a capacitor C2.

In the transistor T1, one of a source and a drain is connected to a terminal D, the other of the source and the drain is connected to a first electrode of the capacitor C1, and a gate is connected to a word line WL. A second electrode of the capacitor C1 is connected to a terminal E.

In the transistor T2, one of a source and a drain is connected to the terminal E, the other of the source and the drain is connected to a first electrode of the capacitor C2, and a gate is connected to the word line WL. A second electrode of the capacitor C2 is connected to the terminal D.

The multiplexer MUX includes a transistor T3 and a transistor T4.

In the transistor T3, one of a source and a drain is connected to an input terminal IN_A, and the other of the source and the drain is connected to an output terminal OUT. A gate of the transistor T3 is connected to the other of the source and the drain of the transistor T1 and the first electrode of the capacitor C1, and such a connection portion is referred to as a node N1.

In the transistor T4, one of a source and a drain is connected to an input terminal IN_B, and the other of the source and the drain is connected to the output terminal OUT. A gate of the transistor T4 is connected to the other of the source and the drain of the transistor T2 and the first electrode of the capacitor C2, and such a connection portion is referred to as a node N2.

Here, the capacitance of the capacitor C1 is set equal to the capacitance of the node N1, and the capacitance of the capacitor C2 is set equal to the capacitance of the node N2. Note that the capacitance of the node N1 includes gate capacitance in the case where the transistor T3 is on in addition to parasitic capacitance between wirings or the like, and the capacitance of the node N2 includes gate capacitance in the case where the transistor T4 is on in addition to parasitic capacitance between wirings or the like.

Next, manners for operating the selection circuit are described with reference to FIG. 2, FIGS. 3A and 3B, and FIG. 4.

FIG. 2 is a timing chart showing potentials of the terminal D, the terminal E, the word line WL, the node N1, the node N2, the input terminal N_A, the input terminal IN_B, and the output terminal OUT.

A low potential and a high potential of the terminal D are set to VD_L (e.g., 0 V) and VD_H (e.g., +1 V), respectively. A low potential and a high potential of the terminal E are set to VE_L (e.g., 0 V) and VE_H (e.g., +1 V), respectively.

A low potential and a high potential of the word line WL are set to VWL_L (e.g., 0 V) and VWL_H (e.g., +2 V), respectively.

A low potential and a high potential of each of the input terminals IN_A and IN_B are set to VIN_L (e.g., 0 V) and VIN_H (e.g., +1 V), respectively. It is preferred that VD_H≦VIN_H, VE_H≦VIN_H, VD_L≧VIN_L, and VE_L≧VIN_L, and more preferably, VD_H=VE_H=VIN_H and VD_L=VE_L =VIN_L. Particularly when VD_H and VE_H are set to be much lower than VIN_H or when VD_L and VE_L are set to be much higher than VIN_L, change in the potential of the word line WL can be made much smaller; therefore, power consumption of a semiconductor device can be reduced.

FIGS. 3A and 3B each show a manner for operating the selection circuit PMUX in a program mode 40 of FIG. 2, and FIG. 4 shows a manner for operating the selection circuit PMUX in a user mode 43 of FIG. 2. Note that the program mode 40 includes a first period 41 in which data is written in the memory MEM and a second period 42 in which a potential of the node N1 or N2 is controlled and the state of the multiplexer MUX is determined The user mode 43 is a period in which given data are input into the input terminals IN_A and IN_B and the data is output in accordance with the state of the multiplexer MUX which is set in advance. [0044]

Note that a threshold voltage of the transistor T1, a threshold voltage of the transistor T2, a threshold voltage of the transistor T3, and a threshold voltage of the transistor T4 are set to Vth_T1, Vth_T2, Vth_T3, and Vth_T4, respectively. Note that Vth_T1 and Vth_T2 are set to the same threshold voltages (e.g., +1 V), and Vth_T3 and Vth_T4 are set to the same threshold voltages, which are lower than Vth_T1 and Vth_T2 (e.g., +0.5 V).

The manner for operating the selection circuit PMUX in the first period 41 of the program mode 40 is described with reference to FIG. 2 and FIG. 3A.

In the first period 41 of the program mode 40, the potentials of the input terminals IN_A and IN_B are each set to a low potential, that is, VIN_L. It seems that the input terminals IN_A and IN_B and the output terminal OUT are insulated by the transistors T3 and T4. However, in the case where the transistors T3 and T4 are normal MOS transistors including silicon, the input terminals IN_A and IN_B and the output terminal OUT can be regarded as conducted therebetween in the time scale longer than 10 milliseconds; therefore, the potential of the output terminal OUT is also VIN_L.

Next, the potential of one of the terminals D and E is set to a high potential and the potential of the other thereof is set to a low potential so that one of the transistors T3 and T4 is turned on. For example, the potential of the terminal D is set to a high potential, that is, VD_H and the potential of the terminal E is set to a low potential, that is, VE_L so that the transistor T3 is turned on and the transistor T4 is turned off. Further, a high potential, that is, VWL_H is applied to the word line WL.

Accordingly, the transistors T1 and T2 are on, the potential of the node N1 corresponds to the high potential of the terminal D, that is, VD_H, and the potential of the node N2 corresponds to the low potential of the terminal E, that is, VE_L. At this stage, the transistor T3 is on and the transistor T4 is off. After that, the potential of the word line WL is set to a low potential, that is, VWL_L.

The manner for operating the selection circuit PMUX in the second period 42 of the program mode 40 is described with reference to FIG. 2 and FIG. 3B.

In the second period 42 of the program mode 40, the transistors T1 and T2 are turned off. Further, the potential of the terminal D and the potential of the terminal E are set to high potentials, that is, VD_H and VE_H, respectively. At this time, the node N1 is in a floating state; therefore, the potential of the node N1 becomes VD_H+α (note that α=(VE_H−VE_L)/2) due to capacitive coupling of the transistor T1 and the capacitor C1. Note that the potential of the node N2 remains at VE_L. At this stage, the transistor T3 is on and the transistor T4 is off.

Through the above manners, the potential of the node N1 or N2 can be made higher than the high potentials of the other components. That is, the potential of the gate of the transistor T3 or T4 included in the multiplexer MUX can be made higher than a potential of a signal input into the input terminal IN_A or IN_B by a voltage higher than or equal to the threshold voltage of the transistor T3 or T4.

Thus, the program mode is terminated.

The manner for operating the selection circuit PMUX in the user mode 43 is described with reference to FIG. 2 and FIG. 4.

In the user mode 43, the potential of the terminal D and the potential of the terminal E are set to high potentials, that is, VD_H and VE_H, respectively, and the potential of the word line WL is set to a low potential, that is, VWL_L to turn off the transistors T1 and T2.

The input terminals IN_A and IN_B are supplied with given potentials, for example, pulses as shown in FIG. 2. At this time, the potential of the node N1 is VD_H+α and the potential of the node N2 is VE_L; thus, the transistor T3 is on and the transistor T4 is off. Therefore, the pulse input into the input terminal IN_B (shown as VIN_B in FIG. 4) is not output from the output terminal OUT, and only the pulse input into the input terminal IN_A (shown as VIN_A in FIG. 4) is output from the output terminal OUT. Here, a potential of a signal output from the other of the source and the drain of the transistor T3 is output to the output terminal OUT substantially without being decreased from the potential of the signal input into the one of the source and the drain of the transistor T3 from the input terminal IN_A as long as VD_H+α≧VIN_H+Vth_T3. In the case of the equation where VD_H=VE_H=VIN_H=+1 V and the equation where VD_L=VE_L=VIN_L=0 V, where α=+0.5 V and both Vth_T3 and Vth_T4 are set to +0.5 V, the high potential of the pulse input from the input terminal IN_A is output from the output terminal OUT while remaining at the same potential.

Note that since the high potential of the node N1 is the same as the high potential of the input terminal IN_A in the case where the potential of the node N1 is the high potential VD_H, a potential lower by Vth_T3, that is, VIN_H−Vth_T3 is output from the output terminal OUT. For example, in the case where both Vth_T3 and Vth_T4 are +0.5 V, a potential lower than the potential of the pulse input from the input terminal IN_A by 0.5 V is output from the output terminal OUT.

Note that the capacitance of the capacitor C1 is preferred to be larger than the capacitance of the node N1 because the increase amount in the potential of the node N1 is increased in such a case. Moreover, the capacitance of the capacitor C2 is preferred to be larger than the capacitance of the node N2 because the increase amount in the potential of the node N2 is increased in such a case. Note that it is preferred to reduce the amount of parasitic capacitance generated in the nodes N1 and N2 by bringing the multiplexer MUX and the memory MEM close to each other because the increase amount in the voltage of the node N1 or N2 in the second period 42 of the program mode is reduced when a large amount of parasitic capacitance is generated in the nodes N1 and N2.

The transistors T1 and T2 included in the memory MEM are each preferred to be a transistor whose channel region is formed in a wide-gap semiconductor. The wide-gap semiconductor is a semiconductor whose band gap is higher than or equal to 2 eV, preferably higher than or equal to 2.5 eV, more preferably higher than or equal to 3 eV. Typical examples of the wide-gap semiconductor include a compound semiconductor such as a gallium nitride, an aluminum nitride, or an indium nitride; a silicon carbide; and an oxide semiconductor. Typical examples of the oxide semiconductor include an In—Ga—Zn-based oxide semiconductor, an indium oxide, an indium tin oxide, an indium gallium oxide, an indium zinc oxide, a tin oxide, a zinc oxide, and a gallium oxide. Note that each of the transistors T1 and T2 is not limited to the transistor whose channel region is formed in the wide-gap semiconductor, and a transistor whose channel region is formed in silicon or the like can be used in the case where a period in which data is held in the nodes N1 and N2 is short. Note that the transistor whose channel region is formed in an oxide semiconductor will be described in detail in Embodiment 3.

A transistor whose channel region is formed in a wide-gap semiconductor has a small off-state current. Further, a transistor whose channel region is formed in an oxide semiconductor has an extremely small off-state current. Typically, the off-state current (here, per unit channel width (1 μm)) at room temperature (25° C.) is less than or equal to 100 zA (1 zA (zeptoampere) is 1×10⁻²¹ A), preferably less than or equal to 10 zA, more preferably less than or equal to 100 yA (1 yA (yoctoampere) is 1×10⁻²⁴ A). Therefore, with the use of the transistor whose channel region is formed in the wide-gap semiconductor, preferably the oxide semiconductor, for each of the transistors T1 and T2, the potentials of the nodes N1 and N2 can be held during a given period (from 10 milliseconds to 10 years). Therefore, it is possible to stop supply of power to the semiconductor device when not used; accordingly, power consumption can be reduced. Moreover, it is not necessary to rewrite data to the nodes N1 and N2 at the start-up; thus, the starting time can be shortened and the power consumption can be reduced.

Note that it is also possible to use a semiconductor other than a wide-gap semiconductor, for example, bulk silicon or a silicon thin film for each of the transistors T1 and T2. In the case where the potentials of the nodes N1 and N2 change with time, the above manners for operating the selection circuit PMUX in the program mode is favorably repeated at appropriate intervals. Note that with the use of the transistor whose channel region is formed in the oxide semiconductor for each of the transistors T1 and T2, it is possible to set longer an interval between the program modes which are repeated and reduce the number of rewriting times. Accordingly, power consumption can be reduced.

In the selection circuit of this embodiment, characteristics higher than or equal to those of a transmission gate as shown in FIG. 12B can be obtained. Accordingly, a p-channel transistor is not necessary and it is possible to reduce the area of the selection circuit. Alternatively, the transistors T3 and T4 shown in FIG. 1 can be provided in the regions of the multiplexer shown in FIG. 12B, where the p-channel transistors need to be provided, and the on-state current of each of the transistors T3 and T4 can be increased by enlarging the channel width of the transistor. Therefore, the response speeds of the transistors T3 and T4 are improved and high-speed operation of the selection circuit can be achieved.

Note that the transfer gate is featured in that rise of a pulse is sharper than that in the transmission gate when the gate potential is sufficiently high, and a period of time in which an intermediate potential (a potential which is neither a high potential nor a low potential) of the pulse exists is sufficiently short. The potential of the output terminal OUT is input into an inverter via some kind of path, and when the intermediate potential of the pulse is input, a shoot-through current is generated between a high-potential node and a low-potential node of the inverter. Therefore, not only an increase of power consumption but also deterioration or breakdown of the inverter is also caused. Accordingly, it is preferred that the period of time in which the intermediate potential is input is short as much as possible.

FIG. 6 shows results of the numerical calculation of the waveforms of pulses output from selection circuits including a transmission gate or a transfer gate. Here, a gradual channel model was used to analyze transistor characteristics. The gate capacitance of the transmission gate and the transfer gate can be ignored because the gate capacitance is sufficiently small compared with capacitance of a load. Further, a pulse input into the selection circuit is considered to be in an ideal state in which the potential is raised from 0 V to +1 V in an infinitely short time.

A curve X indicates a waveform of a pulse output from the transmission gate. A gate potential of an n-channel transistor (threshold voltage: +0.5 V) was set to +1 V, and a gate potential of a p-channel transistor (threshold voltage: −0.5 V) was set to +0 V. The channel width of the n-channel transistor and the channel width of the p-channel transistor were set to be effectively the same. Thus, the channel width of the p-channel transistor is actually three times as large as the channel width of the n-channel transistor.

As apparent from FIG. 6, the curve X is raised linearly. Therefore, a period of time in which an intermediate potential of the pulse exists is relatively long. Note that the intermediate potential ranging from +0.4 V to +0.6 V is favorably assumed. In the transmission gate of FIG. 6, τ1 denotes a period of time in which the intermediate potential exists.

A curve Y indicates a waveform of a pulse output from the transfer gate. A gate potential of an n-channel transistor (threshold voltage: +0.5 V) was set to +1.6 V. The channel width of the n-channel transistor was set to the same as the channel width of the n-channel transistor in the above transmission gate. In the curve Y, the pulse is raised more sharply, and a period of time τ2 in which an intermediate potential exists is about one-third of τ1. Accordingly, occurrence of a shoot-through current can be further suppressed.

A curve Z indicates a waveform of a pulse output from a transfer gate whose channel width is twice as large as the channel width of the transfer gate in the curve Y In the curve Z, the pulse is raised much more sharply, and a period of time in which an intermediate potential exists is about half of τ2. Accordingly, occurrence of a shoot-through current can be further suppressed.

Note that although the two-input and one-output selection circuit is shown as the selection circuit in this embodiment, a 2n-input and one-output selection circuit (n is an integer larger than or equal to 1) or a selection circuit having another number of inputs and another number of outputs can be employed as appropriate.

Embodiment 2

In this embodiment, a semiconductor device including the selection circuit described in Embodiment 1 will be described. Note that here, the semiconductor device includes, in its category, a variety of semiconductor integrated circuits formed using semiconductor elements, such as memory devices, processors, central processing units (CPUs), image processing circuits, digital signal processors (DSPs), microcontrollers, and reconfigurable logic circuits. In addition, the semiconductor device of the present invention also includes, in its category, various devices formed using the above semiconductor integrated circuits, such as RF tags and display devices. The display devices include, in its category, liquid crystal display devices, light-emitting devices having pixels each provided with a light-emitting element typified by an organic light-emitting element (OLED), electronic paper, digital micromirror devices (DMDs), plasma display panels (PDPs), field emission displays (FEDs), and the like. In this embodiment, the reconfigurable logic circuit is described as one embodiment of the semiconductor device.

FIG. 5A is a block diagram showing one embodiment of a reconfigurable logic circuit 50. The reconfigurable logic circuit 50 includes an input/output block (not shown) which is provided on the periphery of the reconfigurable logic circuit 50 and which controls an input signal from the outside and an output signal to the outside, a plurality of logic blocks 51 which have various functions, wirings 55 connected to the logic blocks 51, and a programmable switch 53 which changes a connection state of the wirings 55 by a switch or the like. The logic block 51 includes a plurality of logic elements 57. Further, the reconfigurable logic circuit 50 may further include a multiplier, a phase locked loop (PLL) block, a memory, or the like. The multiplier has a function of multiplying plural pieces of data at a high speed. The PLL block has a function of supplying a clock signal to a circuit in the logic element 57.

FIG. 5B is a block diagram showing one embodiment of the logic element 57. The logic element 57 can change the function of the logic block 51 as appropriate by changing configuration data that are set corresponding to a plurality of circuit configurations (contexts). Note that the configuration data is stored in a memory provided in the logic block 51.

The logic element 57 includes a look-up table LUT including a configuration memory and a selection circuit, a register 61, and a selection circuit PMUX for switching between an output of the register 61 and an output of the look-up table LUT. Here, as the selection circuit PMUX, such a two-input and one-output selection circuit including the memory MEM and the multiplexer MUX as described in Embodiment 1 can be used.

The look-up table LUT performs arithmetic processing on an input signal in response to configuration data and outputs a signal.

Part of the signal output from the look-up table LUT is held in the register 61. A clock signal CLK is input into the register 61, and the signal held in the register 61 is synchronized with the clock signal CLK. Then, the signal is output to the selection circuit PMUX.

The selection circuit PMUX chooses one of the output signal from the look-up table LUT and the output signal from the register 61. In accordance with input of a selection signal, the output signal from the look-up table LUT or the output signal from the register 61 is output from the logic element 57 to another logic element.

In FIG. 5B, the selection circuit PMUX described in Embodiment 1 can be provided between the register 61 and an output terminal OUT. Note that the selection circuit described in Embodiment 1 can be used as the selection circuit provided in the look-up table LUT. Alternatively, the selection circuit described in Embodiment 1 can be provided between the look-up table LUT and the register 61.

Next, another structure of the logic element 57, in which selection circuits PMUX_1, PMUX_2, PMUX_3, and PMUX_4 are provided between the wirings 55 and the look-up table LUT, is described with reference to FIGS. 7A and 7B.

FIG. 7A is an enlarged diagram of a region of the logic element 57, in which the wirings 55 are connected to the look-up table LUT through the selection circuits PMUX_1 to PMUX_4. FIG. 7B is an enlarged diagram of the portion in FIG. 7A, in which the wirings 55 are connected to the selection circuit PMUX_1.

The selection circuit PMUX_1 includes memories MEM_1, MEM_2, and MEM_3. The selection circuit PMUX_1 further includes a transistor T21 whose gate is connected to a node N21 of the memory MEM_(—)

1 and one of whose source and drain is connected to a wiring 55A, a transistor T22 whose gate is connected to the node N21 of the memory MEM_1 and one of whose source and drain is connected to a wiring 55B, a transistor T23 whose gate is connected to a node N22 of the memory MEM_1 and one of whose source and drain is connected to a wiring 55E, and a transistor T24 whose gate is connected to the node N22 of the memory MEM_1 and one of whose source and drain is connected to a wiring 55F.

The selection circuit PMUX_1 still further includes a transistor T31 whose gate is connected to a node N31 of the memory MEM_2 and one of whose source and drain is connected to the other of the source and the drain of the transistor T21, a transistor T32 whose gate is connected to the node N31 of the memory MEM_2 and one of whose source and drain is connected to a wiring 55C, a transistor T33 whose gate is connected to a node N32 of the memory MEM_2 and one of whose source and drain is connected to a wiring 55D, and a transistor T34 whose gate is connected to the node N32 of the memory MEM_2 and one of whose source and drain is connected to the other of the source and the drain of the transistor T24.

The selection circuit PMUX_1 still further includes a transistor T41 whose gate is connected to a node N41 of the memory MEM_3 and one of whose source and drain is connected to the other of the source and the drain of the transistor T22, a transistor T42 whose gate is connected to the node N41 of the memory MEM_3 and one of whose source and drain is connected to the other of the source and the drain of the transistor T32, a transistor T43 whose gate is connected to a node N42 of the memory MEM_3 and one of whose source and drain is connected to the other of the source and the drain of the transistor T33, and a transistor T44 whose gate is connected to the node N42 of the memory MEM_3 and one of whose source and drain is connected to the other of the source and the drain of the transistor T23.

The other of the source and the drain of the transistor T31, the other of the source and the drain of the transistor T41, the other of the source and the drain of the transistor T42, the other of the source and the drain of the transistor T43, the other of the source and the drain of the transistor T44, and the other of the source and the drain of the transistor T34 are connected to the output terminal OUT. The output terminal OUT is connected to input terminals of the look-up table LUT.

As shown in FIG. 7A, the selection circuit PMUX described in Embodiment 1 can be provided between the wirings 55 and the look-up table LUT. Note that the selection circuit PMUX_1 shown in FIG. 7B is a six-input and one-output selection circuit.

According to one embodiment of the present invention, it is possible to reduce power consumption of a semiconductor device including a selection circuit, reduce the area of the selection circuit in the semiconductor device, and downsize the size of the semiconductor device.

Embodiment 3

In this embodiment, a structure of the selection circuit will be described with reference to FIGS. 8A and 8B, FIGS. 9A and 9B, and FIGS. 10A and 10B.

FIGS. 8A and 8B and FIGS. 9A and 9B are plan views illustrating the positions and shapes of main structures in the multiplexer and the memory of the selection circuit. FIG. 10A is a cross-sectional view taken along dot-dash-line A-B in FIGS. 8A and 8B and FIGS. 9A and 9B, and FIG. 10B is a cross-sectional view taken along dot-dash-line C-D in FIGS. 8A and 8B and FIGS. 9A and 9B. Note that in FIGS. 10A and 10B, a transistor 704 a and a transistor 704 b correspond to the transistor T3 and the transistor T4 shown in FIG. 1, respectively, and a transistor 750 corresponds to the transistor T1 shown in FIG. 1. Further, a capacitor 751 corresponds to the capacitor C1 shown in FIG. 1.

The transistors 704 a and 704 b are n-channel transistor (NMOSFET). The transistors 704 a and 704 b are electrically isolated from other elements by a shallow trench isolation (STI) 702. The use of the STI 702 can reduce the generation of a bird's beak in an element isolation region, which is caused in an LOCOS element isolation method, and can reduce the size of the element isolation region. On the other hand, in a semiconductor device in which a transistor is not required to be structurally miniaturized or downsized, the STI 702 is not necessarily formed, and an element isolation means such as LOCOS can be used.

The transistor 704 a includes a channel region in a semiconductor substrate 701, impurity regions 705 (also referred to as a source region and a drain region) which is provided such that the channel region is provided therebetween, a gate insulating film 706 a over the channel region, and a gate electrode 707 a over the gate insulating film 706 a so as to overlap with the channel region. The gate electrode 707 a can be a single layer or a multilayer. Note that the gate electrode 707 a may have a stacked-layer structure of a first conductive film formed using a first material for improving processing accuracy and a second conductive film formed using a second material for reducing resistance.

The transistor 704 b has a structure similar to that of the transistor 704 a and includes a channel region in the semiconductor substrate 701, the impurity regions 705 (also referred to as a source region and a drain region) which is provided such that the channel region is provided therebetween, a gate insulating film 706 b over the channel region, and a gate electrode 707 b over the gate insulating film 706 b so as to overlap with the channel region.

Further, contact plugs 714 a, 714 c, and 714 d are connected to the impurity regions 705 provided in the semiconductor substrate 701. Here, the contact plugs 714 a, 714 c, and 714 d also function as a source electrode and a drain electrode of the transistors 704 a and 704 b. In addition, a contact plug 714 b connects the gate electrode 707 a of the transistor 704 a and a wiring 719 b.

In addition, impurity regions which are different from the impurity regions 705 are provided between the impurity regions 705 and the channel region. These impurity regions function as LDD regions or extension regions for controlling the distribution of an electric field in the vicinity of the channel region, depending on the concentration of an impurity introduced thereto. Sidewall insulating films 710 are provided on sidewalls of the gate electrode 707 a and 707 b. By using the sidewall insulating films 710, the LDD regions or extension regions can be formed.

The transistors 704 a and 704 b can be formed by a known method for manufacturing a MOS (Metal-Oxide-Semiconductor) transistor.

The contact plugs 714 a to 714 d are formed to have a single-layer structure or a stacked-layer structure including any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten and an alloy containing any of these metals as a main component. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order, a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film are stacked in this order, and the like can be given.

The contact plugs 714 a to 714 d can be formed in such a manner that a conductive film is formed by a sputtering method, a CVD method, a plating method, or the like, planarization treatment is performed by a chemical mechanical polishing (CMP) method, an etching method, or the like, and then a surface portion of the conductive film, which is unnecessary, is removed.

The transistors 704 a and 704 b are covered with an insulating film 711. The insulating film 711 can function as a protective film and can prevent impurities from entering the channel region from the outside. In addition, when the insulating film 711 is formed using a material such as silicon nitride by a CVD method, hydrogenation of single crystal silicon can be performed by heat treatment in the case where the single crystal silicon is used for the channel region. When an insulating film having tensile stress or compressive stress is used as the insulating film 711, distortion can be caused in the semiconductor material in the channel region. By application of tensile stress to a silicon material used for the channel region of an n-channel transistor or application of compressive stress to a silicon material used for the channel region of a p-channel transistor, the effect mobility of the transistor can be increased. The insulating film 711 can be formed by a sputtering method or a CVD method.

An insulating film 712 is formed over the insulating film 711. The insulating film 712 can be formed using an insulator such as silicon oxide, silicon oxynitride, silicon nitride oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon oxide to which carbon is added (SiOC), silicon oxide to which fluorine is added (SiOF), tetraethyl orthosilicate (TEOS) which is a silicon oxide made from Si(OC₂H₅)₄, an insulator made from hydrogen silsesquioxane (HSQ), an insulator made from methyl silsesquioxane (MSQ), organosilicate glass (OSG), or an organic polymer-based material. In particular, in the case of advancing miniaturization of a semiconductor device, parasitic capacitance between wirings is significant and signal delay is increased; therefore, the insulating film 712 is preferred to be formed using a material whose relative permittivity k is low, typically less than or equal to 3.0. In addition, CMP treatment is performed after the contact plugs 714 a and 714 b are embedded in the insulating film; therefore, the insulating film needs to have high mechanical strength. As long as their mechanical strength can be secured, the insulating films can be made porous to have a lower dielectric constant. The insulating film 712 is formed by a sputtering method, a CVD method, a coating method including a spin coating method (also referred to as spin on glass (SOG)), or the like.

An insulating film 715 is formed over the insulating film 712. A wiring 719 a, the wiring 719 b, a wiring 719 c, and a wiring 719 d are embedded in the insulating film 715. The wiring 719 a is connected to the input terminal IN_A shown in FIG. 1 and to the transistor 704 a through the contact plug 714 a. The wiring 719 b corresponds to part of the node N1 shown in FIG. 1 and is connected to the gate electrode 707 a of the transistor 704 a through the contact plug 714 b. The wiring 719 c is connected to the output terminal OUT shown in FIG. 1 and to the transistors 704 a and 704 b through the contact plug 714 c. The wiring 719 d is connected to the input terminal IN_B shown in FIG. 1 and to the transistor 704 b through the contact plug 714 d.

The insulating film 715 is formed by a sputtering method, a CVD method, a coating method including a spin coating method, or the like.

The wirings 719 a to 719 d are preferred to be formed using a low-resistance conductive material such as copper or aluminum. By using a low-resistance conductive material, RC delay of signals transmitted through the wirings 719 a to 719 d can be reduced. In the case where copper is used for the wirings 719 a to 719 d, barrier films are preferred to be formed between the insulating film and the wirings 719 a to 719 d in order to prevent copper from dispersing into the channel region of the semiconductor substrate 701. The barrier films can each be formed using, for example, a film of a tantalum nitride, a stacked-layer film of a tantalum nitride and tantalum, a film of a titanium nitride, a stacked-layer film of a titanium nitride and titanium, or the like, but are not limited to the films of these materials as long as their function of preventing diffusion of a wiring material and their adhesion to the wiring material, a base film, or the like are secured. Note that the contact plugs 714 a to 714 d and the wirings 719 a to 719 d may be formed with the same material by a dual damascene method.

FIG. 8A is a top view of the gate electrodes 707 a and 707 b, the contact plugs 714 a to 714 d, and the wirings 719 a to 719 d.

A barrier film 724 and an insulating film 725 are stacked over the insulating film 715 and the wirings 719 a to 719 d. Moreover, contact plugs 723 a and 723 b are embedded in the barrier film 724 and the insulating film 725.

The contact plug 723 a is connected to the wiring 719 b. The contact plugs 723 a and 723 b can be formed in a manner similar to that of the contact plugs 714 a to 714 d.

The barrier film 724 is preferred to be formed using an insulating film having a function of blocking hydrogen, water, and oxygen, which is typically an aluminum oxide film. The barrier film 724 can be formed by a sputtering method or a CVD method.

The insulating film 725 is preferred to be formed using an oxide insulating film from which part of oxygen is released by heating. As such an oxide insulating film from which part of oxygen is released by heating, an oxide insulating film in which the oxygen content is higher than that in the stoichiometric composition is preferred to be used. The oxide insulating film from which part of oxygen is released by heating can make oxygen diffuse into the oxide semiconductor film by heat treatment. Typical examples of the insulating film 725 are films of a silicon oxide, a silicon oxynitride, a silicon nitride oxide, a gallium oxide, a hafnium oxide, an yttrium oxide, an aluminum oxide, an aluminum oxynitride, and the like.

The thickness of the insulating film 725 is larger than or equal to 50 nm, preferably larger than or equal to 200 nm and smaller than or equal to 3000 nm, more preferably larger than or equal to 300 nm and smaller than or equal to 1000 nm. With the use of the thick insulating film 725, the amount of oxygen released from the insulating film 725 can be increased and, in addition, the interface state density at an interface between the insulating film 725 and an oxide semiconductor film to be formed later can be reduced.

Here, “to release part of oxygen by heating” means that the amount of released oxygen is larger than or equal to 1.0×10¹⁸ atoms/cm³, preferably larger than or equal to 3.0×10²⁰ atoms/cm³ in thermal desorption spectroscopy (TDS) on an oxygen atom basis.

In the above structure, the insulating film from which oxygen is released by heating may be an oxygen-excess silicon oxide (SiO_(X) (X>2)). In the oxygen-excess silicon oxide (SiO_(X) (X>2)), the number of oxygen atoms per unit volume is more than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are measured by Rutherford backscattering spectrometry.

The insulating film 725 can be formed by a sputtering method or a CVD method. After the insulating film 725 is formed by a CVD method, oxygen may be added to the insulating film 725.

In FIG. 10A, the transistor 750 and the capacitor 751 are formed over the insulating film 725.

The transistor 750 includes a pair of electrodes 726 a and 726 b over the insulating film 725, an oxide semiconductor film 731 a over the insulating film 725 and the pair of electrodes 726 a and 726 b, a gate insulating film 732 over the oxide semiconductor film 731 a, and a gate electrode 733 a overlapping with the oxide semiconductor film 731 a with the gate insulating film 732 provided therebetween. Moreover, an insulating film 727 covering the gate insulating film 732 and the gate electrode 733 a is included. Note that in FIG. 10B, an oxide semiconductor film 731 b which functions as the channel region of the transistor T2 shown in FIG. 1 is formed over the insulating film 725.

FIG. 8B is a top view of the contact plugs 723 a and 723 b, the pair of electrodes 726 a and 726 b, and a pair of electrodes 726 c and 726 d. FIG. 9A is a top view of the oxide semiconductor films 731 a and 731 b, the gate electrode 733 a, and second electrodes 733 b and 733 c.

Note that parasitic capacitance between the electrode 726 b and the gate electrode 733 a can be made small in such a manner that the pair of electrodes 726 a and 726 b makes contact with the oxide semiconductor film 731 a and the shapes and arrangements of the pair of electrodes 726 a and 726 b and the gate electrode 733 a are made as shown in FIG. 8B and FIG. 9A.

The electrode 726 b functions as a first electrode of the capacitor 751; therefore, the potential of the electrode 726 b (i.e., the potential of the gate electrode 707 a) is decreased due to the off state of the transistor 750. A decrease in the potential of the gate electrode 707 a is not preferred for the characteristics of the selection circuit; thus, it is favorable that such a decrease is made as small as possible. Parasitic capacitance between the electrode 726 b and the gate electrode 733 a can be made small by making the shapes and arrangement of the pair of electrodes 726 a and 726 b and the gate electrode 733 a as described above; therefore, the decrease in the potential of the gate electrode 707 a can be suppressed.

The capacitor 751 includes the electrode 726 b functioning as the first electrode, which is formed over the insulating film 725, the gate insulating film 732, and the second electrode 733 b.

The pair of electrodes 726 a and 726 b and the pair of electrodes 726 c and 726 d can be formed using the same material as the contact plugs 714 a to 714 d. Note that a transparent conductive material containing an indium oxide, a tin oxide, or a zinc oxide may be used for the pair of electrodes 726 a and 726 b and the pair of electrodes 726 c and 726 d. The pair of electrodes 726 a and 726 b and the pair of electrodes 726 c and 726 d can be formed by a sputtering method, a CVD method, a plating method, or the like.

The oxide semiconductor films 731 a and 731 b are preferred to contain at least indium (In) or zinc (Zn). Alternatively, the oxide semiconductor films 731 a and 731 b are preferred to contain both In and Zn. In order to reduce fluctuation in electrical characteristics of the transistors including the oxide semiconductor, the oxide semiconductor is preferred to contain one or more of stabilizers in addition to In and/or Zn.

As examples of the stabilizer, gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like can be given. As other examples of the stabilizer, lanthanoid such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) can be given.

As the oxide semiconductor, for example, the following can be used: a single-component metal oxide such as an indium oxide, a tin oxide, or a zinc oxide; a two-component metal oxide such as an In—Zn-based metal oxide, a Sn—Zn-based metal oxide, an Al—Zn-based metal oxide, a Zn—Mg-based metal oxide, a Sn—Mg-based metal oxide, an In—Mg-based metal oxide, an In—Ga-based metal oxide, or an In—W-based metal oxide; a three-component metal oxide such as an In—Ga—Zn-based metal oxide (also referred to as IGZO), an In—Al—Zn-based metal oxide, an In—Sn—Zn-based metal oxide, a Sn—Ga—Zn-based metal oxide, an Al—Ga—Zn-based metal oxide, a Sn—Al—Zn-based metal oxide, an In—Hf—Zn-based metal oxide, an In—La—Zn-based metal oxide, an In—Ce—Zn-based metal oxide, an In—Pr—Zn-based metal oxide, an In—Nd—Zn-based metal oxide, an In—Sm—Zn-based metal oxide, an In—Eu—Zn-based metal oxide, an In—Gd—Zn-based metal oxide, an In—Tb—Zn-based metal oxide, an In—Dy—Zn-based metal oxide, an In—Ho—Zn-based metal oxide, an In—Er—Zn-based metal oxide, an In—Tm—Zn-based metal oxide, an In—Yb—Zn-based metal oxide, or an In—Lu—Zn-based metal oxide; or a four-component metal oxide such as an In—Sn—Ga—Zn-based metal oxide, an In—Hf—Ga—Zn-based metal oxide, an In—Al—Ga—Zn-based metal oxide, an In—Sn—Al—Zn-based metal oxide, an In—Sn—Hf—Zn-based metal oxide, or an In—Hf—Al—Zn-based metal oxide.

Here, for example, an “In—Ga—Zn-based metal oxide” means an oxide containing In, Ga, and Zn as its main components and there is no particular limitation on the ratio of In, Ga, and Zn. The In—Ga—Zn-based metal oxide may contain a metal element other than In, Ga, and Zn.

Alternatively, a material expressed by InMO₃(ZnO)_(m) (m>0, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one or more metal elements selected from Ga, Fe, Mn, and Co. Alternatively, as the oxide semiconductor, a material expressed by In₂SnO₅(ZnO)_(n) (n>0, n is a natural number) may be used.

For example, an In—Ga—Zn-based metal oxide containing In, Ga, and Zn at an atomic ratio of 1:1:1 (=1/3:1/3:1/3), 2:2:1 (=2/5:2/5:1/5), or 3:1:2 (=1/2:1/6:1/3), or an oxide at an atomic ratio close to the above atomic ratios can be used. Alternatively, an In—Sn—Zn-based metal oxide containing In, Sn, and Zn at an atomic ratio of 1:1:1 (=1/3:1/3:1/3), 2:1:3 (=1/3:1/6:1/2), or 2:1:5 (=1/4:1/8:5/8), or an oxide at an atomic ratio close to the above atomic ratios is favorably used.

However, without limitation to the above compositions at the above ratios, a material with appropriate compositions at appropriate ratios may be used in accordance with needed semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and the threshold voltage). In order to obtain needed semiconductor characteristics, it is preferred that the carrier density, the impurity concentration, the defect density, the atomic ratio between metal elements and oxygen, the interatomic distance, the density, and the like be set appropriately.

For example, high mobility of the In—Sn—Zn-based metal oxide can be obtained relatively easily. However, the mobility of the In—Ga—Zn-based metal oxide can also be increased by reducing the defect density in the bulk.

Further, the energy gap of a metal oxide that can form the oxide semiconductor films 731 a and 731 b is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV. In this manner, as well as being able to withstand a high voltage, the transistor can have a lower off-state current by using an oxide semiconductor having a wide energy gap.

Further, the concentration of hydrogen in the oxide semiconductor films 731 a and 731 b, which is measured by secondary ion mass spectrometry (SIMS), can be set to be lower than 5×10¹⁸ atoms/cm³, preferably lower than or equal to 1×10¹⁸ atoms/cm³, more preferably lower than or equal to 5×10¹⁷ atoms/cm³, further preferably lower than or equal to 1×10¹⁶ atoms/cm³.

Hydrogen contained in the oxide semiconductor films 731 a and 731 b reacts with oxygen bonded to a metal atom to produce water, and a defect is formed in a lattice from which oxygen is released (or a portion from which oxygen is released). In addition, a bond of part of hydrogen and oxygen causes generation of electrons serving as carrier. Thus, the impurities containing hydrogen are reduced as much as possible in the step of forming the oxide semiconductor film, whereby it is possible to reduce the concentration of hydrogen in the oxide semiconductor film. Therefore, when an oxide semiconductor which is highly purified by removing hydrogen as much as possible is used as a channel region, the negative shift in the threshold voltage can be reduced, and the leakage current between a source and a drain of the transistor, typically, the off-state current per channel width (1 μm) can be decreased to several yA/μm to several zA/μm. Accordingly, electrical characteristics of the transistor can be improved.

By the heat treatment, the concentration of hydrogen in the oxide semiconductor films 731 a and 731 b can be reduced.

Further, oxygen vacancies in the oxide semiconductor films 731 a and 731 b can be reduced, whereby a change in the electrical characteristics of the transistor, which is caused by oxygen vacancies, can be reduced, resulting in higher reliability. It is preferred to use an oxide semiconductor film the oxygen content of which is higher than that in the stoichiometric composition for the oxide semiconductor films 731 a and 731 b. It is possible to reduce the oxygen vacancies by adding oxygen to an oxide semiconductor film, and as examples of an oxygen addition method, an ion implantation method, an ion doping method, plasma treatment, and the like can be given. Further, after the insulating film from which oxygen is diffused by heating is provided so as to be in contact with the oxide semiconductor film, oxygen is diffused from the insulating film from which oxygen is diffused by heating into the oxide semiconductor film by the heat treatment; thus, the oxygen vacancies can be reduced.

Note that the oxide semiconductor films 731 a and 731 b may have an amorphous structure, a single crystal structure, or a polycrystalline structure.

As the oxide semiconductor films 731 a and 731 b, a c-axis aligned crystalline oxide semiconductor (also referred to as CAAC-OS) film having crystal parts may be used.

A structure of an oxide semiconductor film is described below.

An oxide semiconductor film is classified roughly into a single-crystal oxide semiconductor film and a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, and the like.

The amorphous oxide semiconductor film has disordered atomic arrangement and no crystalline component. A typical example thereof is an oxide semiconductor film in which no crystal part exists even in a microscopic region, and the whole of the film is amorphous.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Thus, the microcrystalline oxide semiconductor film has a higher degree of atomic order than the amorphous oxide semiconductor film. Hence, the density of defect states of the microcrystalline oxide semiconductor film is lower than that of the amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits inside a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film. The CAAC-OS film is described in detail below.

In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.

On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.

From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film.

A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO₄, six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56°.

According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.

In this specification, a term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, a term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.

Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.

Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depending on regions.

Note that when the CAAC-OS film with an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. It is preferred that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ do not appear at around 36°.

In a transistor using the CAAC-OS film, change in electric characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has high reliability.

Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

Further, the oxide semiconductor films 731 a and 731 b may have a structure in which a plurality of oxide semiconductor films is stacked. For example, the oxide semiconductor films 731 a and 731 b may have a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film which are formed using metal oxides with different compositions at different ratios. For example, the first oxide semiconductor film may be formed using any of two-component metal oxide, a three-component metal oxide, and a four-component metal oxide, and the second oxide semiconductor film may be formed using any of these which is different from the metal oxide used for the first oxide semiconductor film.

The constituent elements of the first oxide semiconductor film and the second oxide semiconductor film are made to be the same but the composition ratio of the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be made to be different. For example, the first oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:1:1, and the second oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 3:1:2. Alternatively, the first oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:3:2, and the second oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 2:1:3.

At this time, one of the first oxide semiconductor film and the second oxide semiconductor film, which is closer to the gate electrode (on a channel side), is preferred to contain In and Ga at a proportion where In>Ga. The other oxide semiconductor film which is farther from the gate electrode (on a back channel side) is preferred to contain In and Ga at a proportion where In≦Ga.

Further, the oxide semiconductor films 731 a and 731 b may have a four-layer structure of a first oxide semiconductor film, a second oxide semiconductor film, a third oxide semiconductor film, and a fourth oxide semiconductor film, in which the constituent elements thereof are made the same but the composition ratio of the constituent elements of the first oxide semiconductor film, the second oxide semiconductor film, the third oxide semiconductor film, and the fourth oxide semiconductor film is made different. For example, the first oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:3:2, the second oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:1:1, the third oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 3:1:2, and the fourth oxide semiconductor film may contain In, Ga, and Zn at an atomic ratio of 1:3:2.

An oxide semiconductor film which contains less In than Ga and Zn at an atomic ratio, typically, the first oxide semiconductor film and the fourth oxide semiconductor film each containing In, Ga, and Zn at an atomic ratio of 1:3:2, has a higher insulating property than an oxide semiconductor film containing In, Ga, and Zn each at the same atomic ratio, typically, the second oxide semiconductor film, and an oxide semiconductor film containing more In than Ga and Zn at an atomic ratio, typically, the third oxide semiconductor film. Further, when the first oxide semiconductor film and the fourth oxide semiconductor film each containing In, Ga, and Zn at an atomic ratio of 1:3:2 have an amorphous structure, the insulating properties are further improved. Accordingly, the second oxide semiconductor film and the third oxide semiconductor film each serve as a channel region, and the first oxide semiconductor film and the fourth oxide semiconductor film each serve as a gate insulating film.

Since the constituent elements of the first oxide semiconductor film, the second oxide semiconductor film, the third oxide semiconductor film, and the fourth oxide semiconductor film are the same, the first oxide semiconductor film and the fourth oxide semiconductor film have fewer trap levels at the interface with the second oxide semiconductor film and the interface with the third oxide semiconductor film, respectively. Therefore, when the oxide semiconductor films 731 a and 731 b each have the above structure, the amount of change in the threshold voltage of the transistor due to a change over time or a BT photostress test can be reduced.

In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the In content in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Therefore, an oxide containing In and Ga at a proportion where In>Ga has higher mobility than an oxide containing In and Ga at a proportion where In≦Ga. Further, in Ga, the formation energy of an oxygen vacancy is larger and thus an oxygen vacancy is less likely to occur, than in In; therefore, the oxide containing In and Ga at a proportion where In≦Ga has more stable characteristics than the oxide containing In and Ga at a proportion where In>Ga.

An oxide semiconductor containing In and Ga at a proportion where In>Ga is used on the channel side and an oxide semiconductor containing In and Ga at a proportion where In≦Ga is used on the back channel side, so that field-effect mobility and reliability of the transistor can be further improved.

Further, the oxide semiconductor films 731 a and 731 b may be formed by employing a stacked-layer structure of oxide semiconductors having different crystallinity. That is, the oxide semiconductor films may be formed using any of a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, and a CAAC-OS, as appropriate. When the oxide semiconductor films 731 a and 731 b each have a stacked-layer structure part of which includes an amorphous oxide semiconductor, internal stress or external stress of the oxide semiconductor films 731 a and 731 b is relieved, fluctuation in transistor characteristics is reduced, and the reliability of the transistor can be further improved.

Each thickness of the oxide semiconductor films 731 a and 731 b is preferably larger than or equal to 1 nm and smaller than or equal to 100 nm, more preferably larger than or equal to 1 nm and smaller than or equal to 30 nm, still more preferably larger than or equal to 1 nm and smaller than or equal to 50 nm, further preferably larger than or equal to 3 nm and smaller than or equal to 20 nm.

The concentration of alkali metal or alkaline earth metal in each of the oxide semiconductor films 731 a and 731 b is preferably lower than or equal to 1×10¹⁸ atoms/cm³, more preferably lower than or equal to 2×10¹⁶ atoms/cm³. This is because, when alkali metal or alkaline earth metal is bonded to an oxide semiconductor, some of the alkali metal or the alkaline earth metal generates carriers and cause an increase in the off-state current of the transistor.

The oxide semiconductor films 731 a and 731 b may contain nitrogen at a concentration lower than or equal to 5×10¹⁸ atoms/cm³.

The oxide semiconductor films 731 a and 731 b can be formed by a sputtering method, a coating method, a printing method, a pulsed laser deposition method, or the like.

It is sufficient that the gate insulating film 732 be formed to have a stacked-layer structure or a single-layer structure using any of a silicon oxide, a silicon oxynitride, a Ga—Zn-based metal oxide, an aluminum oxide, an aluminum oxynitride, a gallium oxide, a gallium oxynitride, an yttrium oxide, an yttrium oxynitride, a hafnium oxide, a hafnium oxynitride, and the like. The gate insulating film 732 can be formed by a sputtering method or a CVD method.

The gate electrode 733 a and the second electrodes 733 b and 733 c can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metal elements as a component; an alloy containing any of these metal elements in combination; or the like. Further, one or more metal elements selected from manganese or zirconium may be used. The gate electrode 733 a may have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given. Alternatively, a film, an alloy film, or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used.

The gate electrode 733 a and the second electrodes 733 b and 733 c can also be formed using a light-transmitting conductive material such as an indium tin oxide, an indium oxide containing a tungsten oxide, an indium zinc oxide containing a tungsten oxide, an indium oxide containing a titanium oxide, an indium tin oxide containing a titanium oxide, an indium zinc oxide, or an indium tin oxide to which a silicon oxide is added. It is also possible to have a stacked-layer structure formed using the above light-transmitting conductive material and the above metal element. The gate electrode 733 a and the second electrodes 733 b and 733 c can be formed by using a formation method similar to that of the pair of electrodes 726 a and 726 b as appropriate.

Further, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, an In—Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a film of a metal nitride (such as InN or ZnN), or the like is preferred to be provided between the gate electrode 733 a and the gate insulating film 732. These films each have a work function higher than or equal to 5 eV, preferably higher than or equal to 5.5 eV, which is higher than the electron affinity of an oxide semiconductor; thus, the threshold voltage of a transistor including the oxide semiconductor can be shifted in the positive direction. Accordingly, a switching element having what is called normally-off characteristics can be obtained. For example, in the case of using an In—Ga—Zn-based oxynitride semiconductor film, an In—Ga—Zn-based oxynitride semiconductor film having a higher nitrogen concentration than at least the oxide semiconductor films 731 a and 731 b, specifically, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration higher than or equal to 7 at. % is used.

It is sufficient that the insulating film 727 be formed to have a single-layer structure or a stacked-layer structure using one or more of a silicon oxide, a silicon oxynitride, a silicon nitride oxide, a silicon nitride, an aluminum oxide, an aluminum oxynitride, an aluminum nitride oxide, an aluminum nitride, and the like.

An insulating film 728 is formed over the insulating film 727. Contact plugs 735 a and 735 d penetrating the insulating films 727 and 728 and the gate insulating film 732, and contact plugs 735 b and 735 c penetrating the insulating films 727 and 728 are formed. An insulating film 730 is formed over the insulating film 728 and the contact plugs 735 a to 735 d, and wirings 737 a and 737 b are embedded in the insulating film 730.

FIG. 9B is a top view of the contact plugs 735 a to 735 d and the wirings 737 a and 737 b.

The wiring 737 a and the wiring 737 b are connected to the terminal D and the terminal E shown in FIG. 1, respectively. The wiring 737 a is connected to the transistor 750 through the contact plug 735 a, and the wiring 737 b is connected to the capacitor 751 through the contact plug 735 b. The transistor 750 and the capacitor 751 are connected to each other through the electrode 726 b.

Note that the insulating film 728 can be formed in a manner similar to that of the insulating film 712. The contact plugs 735 a and 735 b can be formed in a manner similar to that of the contact plugs 714 a to 714 d. The insulating film 730 can be formed in a manner similar to that of the insulating film 715. The wirings 737 a and 737 b can be formed in a manner similar to that of the wirings 719 a to 719 d.

A barrier film 740 is provided over the wirings 737 a and 737 b. The barrier film 740 can be formed in a manner similar to that of the barrier film 724.

Note that for the transistor 750, a structure in which a pair of electrodes is provided between the oxide semiconductor film 731 a and the gate insulating film 732 can be employed instead of the structure in FIGS. 10A and 10B.

In addition, although a top-gate structure is employed for the transistor 750 illustrated in FIG. 10A, a bottom-gate structure can be employed as appropriate. A transistor having a bottom-gate structure is described with reference to FIG. 11.

FIG. 11 illustrates another embodiment of the selection circuit illustrated in FIGS. 10A and 10B in portions from the barrier film 724 to the barrier film 740.

The insulating film 725 is formed over the barrier film 724. Moreover, a contact plug 723 is embedded in the barrier film 724 and the insulating film 725.

A transistor 780 and a capacitor 781 are formed over the insulating film 725.

The transistor 780 includes a first gate electrode 761 a over the insulating film 725, a first gate insulating film 765 over the first gate electrode 761 a, an oxide semiconductor film 767 over the first gate insulating film 765, a pair of electrodes 769 a and 769 b in contact with the oxide semiconductor film 767, a second gate insulating film 771 over the oxide semiconductor film 767 and the pair of electrodes 769 a and 769 b, and a second gate electrode 773 a overlapping with the oxide semiconductor film 767 with the second gate insulating film 771 provided therebetween. Moreover, an insulating film 775 covering the second gate insulating film 771 and the second gate electrode 773 a is included.

An insulating film 760 is formed over the insulating film 725. The first gate electrode 761 a and wirings 761 b and 761 c are embedded in the insulating film 760.

The wiring 761 b and the wiring 761 c are in contact with the electrode 769 a and the electrode 769 b, respectively.

The capacitor 781 includes the electrode 769 b functioning as a first electrode, which is formed over the insulating film 760 and the wiring 761 c, the second gate insulating film 771, and a second electrode 773 b.

The transistor 780 is connected to the wiring 737 a through the contact plug 735 a. The capacitor 781 is connected to the wiring 737 b through the contact plug 735 b. The transistor 780 and the capacitor 781 are connected to each other through the electrode 769 b.

The first gate electrode 761 a and the wirings 761 b and 761 c can be formed in a manner similar to that of the gate electrode 733 a in FIGS. 10A and 10B.

The first gate insulating film 765 and the oxide semiconductor film 767 can be formed in a manner similar to that of the gate insulating film 732 and the oxide semiconductor films 731 a and 731 b in FIGS. 10A and 10B, respectively.

The pair of electrodes 769 a and 769 b can be formed in a manner similar to that of the pair of electrodes 726 a and 726 b in FIG. 10A.

The second gate insulating film 771 can be formed in a manner similar to that of the gate insulating film 732 in FIGS. 10A and 10B.

The second gate electrode 773 a and the second electrode 773 b can be formed in a manner similar to that of the gate electrode 733 a in FIGS. 10A and 10B.

The insulating film 775 can be formed in a manner similar to that of the insulating film 727 in FIGS. 10A and 10B.

The transistor 780 of this embodiment has the first gate electrode 761 a and the second gate electrode 773 a facing each other with the oxide semiconductor film 767, the first gate insulating film 765, and the second gate insulating film 771 provided therebetween. By application of different potentials to the first gate electrode 761 a and the second gate electrode 773 a, the threshold voltage of the transistor 780 can be controlled, and in a preferable manner, the negative shift in the threshold voltage can be suppressed. Alternatively, when the same potential is applied to the first gate electrode 761 a and the second gate electrode 773 a, the on-state current of the transistor 780 can be increased.

Note that for the transistor 780, a structure in which a pair of electrodes is provided between the oxide semiconductor film 767 and the first gate insulating film 765 can be employed instead of the structure in FIG. 11.

Although the transistor 780 includes the first gate electrode 761 a and the second gate electrode 773 a, a transistor including only the first gate electrode 761 a may be used.

As described above, a semiconductor device including the selection circuit can be fabricated.

Such a semiconductor device is not limited to the above structure and can be changed as desired unless it deviates from the spirit of the present invention. For example, although one layer including the wirings, which is provided between the transistor 750 and the transistor 704 a and 704 b, is provided in FIGS. 10A and 10B, the number of the layers including the wirings can be two or more. Alternatively, elements can be directly connected to each other only by a contact plug without a wiring. In that case, a through-silicon via (TSV) technique can also be used, for example. In addition, although a material such as copper is embedded in an insulating film to form a wiring in the above description, a wiring having a three-layer structure of, for example, a barrier film, a wiring material layer, and a barrier film may be obtained by patterning through a photolithography process.

This embodiment can be combined with any of the above embodiments as appropriate.

This application is based on Japanese Patent Application serial No. 2012-119633 filed with the Japan Patent Office on May 25, 2012, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A method for driving a semiconductor device, the semiconductor device comprising: a memory comprising a first transistor, a first capacitor, a second transistor, and a second capacitor; a multiplexer comprising a third transistor and a fourth transistor; a first input terminal configured to input a first signal, and a second input terminal configured to input a second signal; and an output terminal configured to output the first signal or the second signal, wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor, wherein one of a source and a drain of the second transistor is electrically connected to the second capacitor, wherein a source of the third transistor is electrically connected to the first input terminal, and a drain of the third transistor is electrically connected to the output terminal, and wherein a source the fourth transistor is electrically connected to the second input terminal, and a drain of the fourth transistor is electrically connected to the output terminal, the method comprising the steps of: holding a first potential in one of a first node and a second node; holding a second potential in the one of the first node and the second node; inputting the first signal into the first input terminal and the second signal into the second input terminal, after holding the second potential; and outputting the first signal or the second signal from the output terminal, wherein the first node is electrically connected to the one of the source and the drain of the first transistor, the first capacitor, and a gate of the third transistor, wherein the second node is electrically connected to the one of the source and the drain of the second transistor, the second capacitor, and a gate of the fourth transistor, and wherein the second potential is higher than the first potential.
 2. The method for driving the semiconductor device according to claim 1, wherein the first potential in the one of the first node and the second node is held by inputting a third signal into the other of the source and the drain of the first transistor and inputting a fourth signal into the other of the source and the drain of the second transistor, whereby one of the third transistor and the fourth transistor is turned on, and wherein the second potential in the one of the first node and the second node is held by inputting a fifth signal into the other of the source and the drain of the first transistor and inputting a sixth signal into the other of the source and the drain of the second transistor, wherein the third signal and the fourth signal are complementary to each other, and wherein the fifth signal and the sixth signal have a same potential.
 3. The method for driving the semiconductor device according to claim 2, further comprising the step of: holding a third potential in the other of the first node and the second node, before inputting the first signal and the second signal, wherein the third potential turns off the other of the third transistor and the fourth transistor.
 4. A method for driving a semiconductor device, the semiconductor device comprising: a memory comprising a first transistor, a first capacitor, a second transistor, and a second capacitor; a multiplexer comprising a third transistor and a fourth transistor; a first input terminal configured to input a first signal, and a second input terminal configured to input a second signal; and an output terminal configured to output the first signal or the second signal, wherein one of a source and a drain of the first transistor is electrically connected to the first capacitor, wherein one of a source and a drain of the second transistor is electrically connected to the second capacitor, wherein a source of the third transistor is electrically connected to the first input terminal, and a drain of the third transistor is electrically connected to the output terminal, and wherein a source of the fourth transistor is electrically connected to the second input terminal, and a drain of the fourth transistor is electrically connected to the output terminal, the method comprising the steps of: holding a first potential in a first node; holding a second potential in a second node; inputting the first signal into the first input terminal and the second signal into the second input terminal, after holding the first potential and the second potential; and outputting the first signal from the output terminal, wherein the first node is electrically connected to the one of the source and the drain of the first transistor, the first capacitor, and a gate of the third transistor, wherein the second node is electrically connected to the one of the source and the drain of the second transistor, the second capacitor, and a gate of the fourth transistor, wherein the first potential is higher than a maximum potentials of the first signal and the second signal, wherein the first potential can turn on the third transistor, regardless of an input of the first signal and the second signal, and wherein the second potential can turn off the fourth transistor, regardless of an input of the first signal and the second signal.
 5. The method for driving the semiconductor device according to claim 1, the semiconductor device further comprising: a first terminal electrically connected to the other of the source and the drain of the first transistor; and a second terminal electrically connected to the other of the source and the drain of the second transistor, wherein the first terminal is configured to apply a voltage to the first node, and the second terminal is configured to apply a voltage to the second node.
 6. The method for driving the semiconductor device according to claim 4, the semiconductor device further comprising: a first terminal electrically connected to the other of the source and the drain of the first transistor; and a second terminal electrically connected to the other of the source and the drain of the second transistor, wherein the first terminal is configured to apply a voltage to the first node, and the second terminal is configured to apply a voltage to the second node.
 7. The method for driving the semiconductor device according to claim 1, wherein each of off-state currents of the first transistor and the second transistor is less than or equal to 100 zA.
 8. The method for driving the semiconductor device according to claim 4, wherein each of off-state currents of the first transistor and the second transistor is less than or equal to 100 zA.
 9. The method for driving the semiconductor device according to claim 1, wherein a capacitance of the first capacitor is larger than a parasitic capacitance of the first node.
 10. The method for driving the semiconductor device according to claim 4, wherein a capacitance of the first capacitor is larger than a parasitic capacitance of the first node.
 11. The method for driving the semiconductor device according to claim 1, wherein a capacitance of the second capacitor is larger than a parasitic capacitance of the second node.
 12. The method for driving the semiconductor device according to claim 4, wherein a capacitance of the second capacitor is larger than a parasitic capacitance of the second node.
 13. The method for driving the semiconductor device according to claim 1, wherein each of channel regions of the first transistor and the second transistor comprises an oxide semiconductor.
 14. The method for driving the semiconductor device according to claim 4, wherein each of channel regions of the first transistor and the second transistor comprises an oxide semiconductor.
 15. The method for driving the semiconductor device according to claim 1, wherein each of channel regions of the first transistor and the second transistor comprises a silicon film.
 16. The method for driving the semiconductor device according to claim 4, wherein each of channel regions of the first transistor and the second transistor comprises a silicon film.
 17. A display device driven by the method for driving the semiconductor device according to claim
 1. 18. A display device driven by the method for driving the semiconductor device according to claim
 4. 19. A central processing units driven by the method for driving the semiconductor device according to claim
 1. 20. A central processing units driven by the method for driving the semiconductor device according to claim
 4. 